The present disclosure relates to a semiconductor integrated circuit provided with an electrostatic discharge (ESD) protection device.
In recent years, semiconductor integrated circuits have been increasingly enhanced in the scale of integration in parallel with implementation of finer and higher-density devices, and hence have become susceptible to damages caused by electrostatic discharge (hereinafter, referred to as a “surge”). For example, the possibility has increased that devices such as input circuits, output circuits, input/output circuits, and internal circuits may be broken due to surges entering via pads for external connection (external pads), degrading the performance of the devices. For this reason, semiconductor integrated circuits are provided with ESD protection devices that are placed between external pads and any of input circuits, output circuits, input/output circuits, and internal circuits, for protection of such circuits against surges.
Also, in a semiconductor integrated circuit, with increase in the number of circuit blocks for higher functionality and with decrease in power consumption, the number of different power supplies used in the semiconductor integrated circuit has been sharply increasing. Signals are transferred between circuit blocks that use different power supplies in the semiconductor integrated circuit. Hence, to prevent surge-caused breakage of circuit portions responsible for transfer of signals between circuit blocks that use different power supplies, an ESD protection circuit must be provided between different power supplies. The relationship between the number of different power supplies and the number of ESD protection circuits (theoretical value) required to be placed is expressed by N=P×(P−1)÷2. For example, when the number of different power supplies is 20, 190 ESD protection circuits are required.
However, since ESD protection circuits do not function at all during normal operation of a semiconductor integrated circuit, it is strongly desired to reduce the area of the ESD protection circuits as much as possible to reduce the cost of the semiconductor integrated circuit.
FIG. 5 is a view showing a circuit configuration of a conventional ESD protection device including a plurality of ESD protection circuits, and FIG. 6 is a view showing a layout (upper part) and cross section (lower part) of the conventional ESD protection device. FIG. 5 is shown in Japanese Patent Publication No. H06-104721. As shown in FIG. 5, the conventional ESD protection device includes a first protection circuit 200 placed between a first external terminal 100 and a second external terminal 101, a second protection circuit 201 placed between the second external terminal 101 and a third external terminal 102, and a third protection circuit 202 placed between the third external terminal 102 and the first external terminal 100. The first, second, and third protection circuits 200, 201, and 202 are each constructed of an N-channel MOS transistor (hereinafter, referred to as an NMOS transistor). The first, second, and third external terminals 100, 101, and 102 receive power supply voltages different from one another.
As shown in FIG. 6, the first, second, and third protection circuits 200, 201, and 202 are all formed on a p-type well 122 that is formed on a semiconductor substrate 120. Element isolation regions 110 constructed of shallow trench isolation (STI) and the like respectively surround the first, second, and third protection circuits 200, 201, and 202 individually. Also, guard rings 400, 401, 402 respectively surround the first, second, and third protection circuits 200, 201, and 202 individually. The guard rings 400, 401, and 402 are formed in an upper portion of the p-type well 122 and include a p-type impurity at a density higher than the p-type well 122.
If a surge enters from the first external terminal 100, the charge of the surge is released to the second external terminal 101 via the first protection circuit 200 and to the third external terminal 102 via the third protection circuit 202. Likewise, if a surge enters from the second external terminal 101, the charge of the surge is released to the first external terminal 100 via the first protection circuit 200 and to the third external terminal 102 via the second protection circuit 201. If a surge enters from the third external terminal 102, the charge of the surge is released to the second external terminal 101 via the second protection circuit 201 and to the first external terminal 100 via the third protection circuit 202.
With the configuration and operation as described above, the conventional ESD protection device can protect circuits to be protected such as input circuits, output circuits, input/output circuits, and internal circuits.